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ASIC & FPGA Design Engineer Sr Stf - E5 at Lockheed Martin, Orlando, FL

ASIC & FPGA Design Engineer Sr Stf - E5 at Lockheed Martin in Orlando, FL. Full-time. $148,300 to $275,500 a year. Apply with swipeandhired.

You will be the ASIC & FPGA Design Engineer Sr Stf for the Programmable Logic Design organization at Lockheed Martin. Lockheed Martin Missiles and Fire Control (MFC) is a recognized designer, developer, and manufacturer of precision engagement aerospace and defense systems for the U.S. and allied militaries. This role is suited for an accomplished FPGA/ASIC professional who can operate as a player/coach—personally driving the most challenging architecture, design, and verification work while leading cross-discipline IPTs, mentoring staff-level engineers, and shaping programmable logic technical strategy across multiple programs.

What You Will Be Doing
As the ASIC & FPGA Design Engineer Sr Stf you will serve as the principal technical lead for programmable logic across a portfolio of missile, sensor, and weapon-system programs, operating as a hands-on technical leader while directly shaping the next generation of FPGA/ASIC engineering talent at MFC. Your responsibilities will include:

Driving end-to-end FPGA/ASIC architecture decisions across multiple programs, from requirements capture through synthesis, place-and-route, and timing/power closure.
Owning the technical strategy for device selection, IP reuse, and toolchain standardization (AMD Vivado/Vitis, Altera Quartus, and equivalent) across the programmable logic portfolio.
Leading complex verification strategy development, including UVM-based testbench architecture and coverage closure, for safety- and mission-critical FPGA/ASIC designs.
Directing implementation of NSA algorithm architectures (e.g., AES, counter mode) and RF waveform processing chains, including Simulink/HDL Coder-based model-based design flows.
Chairing or leading Design Assurance reviews (PDR, CDR, TRR) across multiple concurrent programs and driving corrective action to closure.
Owning the Design Architecture Development process at the program level, including risk identification, mitigation planning, and schedule/technical performance tracking.
Mentoring and developing mid-career and staff-level FPGA/ASIC engineers, establishing coding standards, design guidelines, and lessons learned across the organization.
Leading or contributing to competitive captures and IRAD strategy, including technical volume authoring, basis-of-estimate development, and technology maturation roadmaps.
Representing programmable logic engineering in customer-facing engagements, technical interchange meetings (TIMs), and program milestone reviews.
Coordinating configuration control strategy (GitLab or equivalent) and design documentation standards across multiple concurrent FPGA/ASIC efforts.

Why Join Us
Do you want to be part of a company culture that empowers employees to think big, lead with a growth mindset, and make the impossible a reality? We provide the resources and give you the flexibility to enable inspiration and focus. If you have the passion and courage to dream big, work hard, and have fun doing what you love then we want to build a better tomorrow with you.
We offer flexible work schedules to comprehensive benefits investing in your future and security. Learn more about Lockheed Martin's comprehensive benefits package here .

Further Information About This Opportunity:
This position is in Orlando.

Citizenship / Clearance:
MUST BE A U.S. CITIZEN – This position is located at a facility that requires special access. An active DoD Secret clearance is required for this role but is not required to start.

Basic Qualifications

Bachelor of Science degree in Electrical Engineering or a closely related STEM field from an accredited university; Master's degree strongly preferred.
Minimum 8 years of professional experience with FPGA/ASIC design and verification or a closely related discipline (or 6+ years with a Master's degree in a related STEM field).
Demonstrated experience as the FPGA/ASIC technical lead on a major effort, with responsibility for architecture, design, verification, and integration of complex digital systems.
Deep expertise across multiple programmable logic domains, including: FPGA/ASIC architecture and requirements decomposition from system through gate level; advanced HDL design (VHDL, Verilog, SystemVerilog) and Universal Verification Methodology (UVM); timing closure, clock domain crossing, and power/thermal optimization across multiple FPGA vendor families; NSA algorithm implementation and RF waveform processing, including Simulink/HDL Coder flows; and Design Assurance / DAR processes and formal review gates (PDR, CDR, TRR).
Expert-level proficiency with Xilinx/AMD (including Versal), Altera/Intel, and Microsemi/Microchip toolchains and part families.
Demonstrated ability to lead technical teams, mentor staff engineers, and influence technical direction across organizational boundaries.
Experience supporting proposal development, including technical volume authoring, basis-of-estimate, and competitive technical strategy on major FPGA/ASIC captures.
Excellent verbal and written communication skills with demonstrated ability to brief executive leadership, customers, and non-technical audiences.
Must be a US Citizen; must possess or be able to obtain a DoD Secret clearance.

Desired Skills

Active DoD Secret or Top Secret clearance.
Master's degree or PhD in Electrical Engineering or related STEM field.
Cross-Business Area engagement and large-program technical-lead experience.
LM/MFC design experience and missile/sensor program experience.
Experience with the MFC Design Assurance / DAR process at the program-ownership level.
Experience with safety boards and range safety requirements (RCC 319, MIL-STD-1316, JOTP-051, MIL-STD-1901).
Deep experience with SystemVerilog, Verilog, C/C++, MATLAB/Simulink; Synopsys Synplify, Synopsys VCS, NCSim, ChipScope tool sets.
Experience leading implementation of NSA algorithms (e.g., AES, counter mode) and RF waveform implementations.
Experience with EOIR image processing techniques and missile/processor interfaces.
Demonstrated ability to lead FPGA trade-off studies focusing on device utilization, power, and thermal optimization across a program portfolio.
Successful proposal/capture leadership experience (BOE, technical volume authoring, technical strategy) on major programmable logic programs.
Demonstrated effectiveness as a "player/coach" working with minimal supervision in fast-paced, multi-program environments.
Strong mentoring track record with mid-career and staff FPGA/ASIC engineers.
Experience with advanced digital disciplines (high-speed SerDes, RFSoC integration, hardware security, ML inference acceleration on FPGA).
Active participation in professional societies and technical conference involvement.

Pay Information
Full-Time Salary Range: $148300.00 - $275500.00
At Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow—both professionally and personally.
The salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer.
Benefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability.

Annual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics.
For (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.